Many power electronic circuits consist of inverter legs or arms. An inverter leg is shown in FIG. 1. Each inverter leg consists of two power switches (SI and S2) connected across a dc voltage rail. This switch arrangement across a dc voltage rail is also known as a totem-pole configuration. Each switch has an anti-parallel diode (D1 or D2), which can be part of the switch structure in a power mosfet or an externally connected diode. In addition, there is also capacitance across the switch and diode. This o capacitance (C) arises from the inherent capacitance of the switch and diode. In some applications, however, an additional capacitor may be connected across the switch to increase the capacitance if more capacitance is needed for achieving soft switching.
Usually, the node between S1 and S2 is connected to the load circuit (Fig. 1). The two switches are turned on and off in a complimentary manner with a dead time in between. This means that only one switch is turned on at any time. Between the change of switching states, both switches are not turned on for a short period of time that is known as the dead time. Usually, this dead time is a small portion of the switching period. Two inverter legs can be used to form a single-phase full-bridge inverter (FIG. 2). The inverter leg can be used to form a half-bridge inverter as shown in FIG. 3(a) and FIG. 3(b). Capacitor Cb is simply a dc voltage blocking capacitor (FIG. 3(b)). The function of the inverter circuits are to generate an ac voltage from the do votlage supply and apply this ac voltage across the load which may be an energy-consuming component (ie a resistive load) or an energy-storing component such as a capacitor and inductor forming a resonant tank.
Examples of typical loads are shown in FIG. 4 and FIG. 5. In FIG. 4, the overall load consists of a dc voltage blocking capacitor, a resonant inductor, a resonant capacitor and an equivalent resistive load. This is a commonly used circuit for an electronic ballast for a lamp and the resistive load represents the energy consuming lamp. The equivalent resistive load can also be a transformer coupled circuit with the energy-consuming load connected on the secondary transformer circuit via a rectifier (such as the system for a switched mode power supply). FIG. 5 shows multi-resonant circuit with an energy-consuming load. This multi-resonant circuit is an alternative electronic ballast circuit for a high-intensity-discharge (HID) lamp, in which Lr2 and Cr form a relatively low-frequency (e.g. 50 kHz) resonant tank to create a high voltage to ignite the HID lamp and Lrl and Cr form a relatively high-frequency (e.g. 400 kHz) resonant tank for operating the lamp under steady-state conditions. Here Lr2>Lrl.
To understand the problems faced by existing technology, existing soft-switching techniques for power electronic circuits with inverter leg or legs will be described, using the half-bridge circuit in FIG. 4 as an example. The directions of the load current Iinput and load voltage Vinput as indicated in FIG. 4 are assigned as positive for the following description.
In the example of FIG. 4, the dc blocking capacitor Cb eliminates the dc component of the ac voltage generated by the inverter leg. The resonant tank consists of Lr and Cr and the dominant resonant frequency is fr=½πsqrt(LrCr). If the switching frequency (fs) of the AC rectangular voltage generated by the inverter circuit is higher than fr, the overall load including the resonant tank and resistive load is more inductive than capacitive. In this case (fs>fr), the overall load is considered as inductive and the current Iz is lagging behind the applied ac voltage Vz as shown in FIG. 6(a). On the other hand, if fs<fr, the overall load is capacitive and the current Iinput is leading the applied voltage Vinput as shown in FIG. 6(b).
FIG. 7 shows three typical switching trajectories of a power switch. The y-axis is the current through the switch and the x-axis is the voltage across the switch. During the transition periods of the turn-on or turn-off processes, a power switch will withstand high transitional voltage (across the switch) and current (through the switch). This is called hard switching. Hard switching not only leads to switching loss and stress, but more importantly causes switching transients or spikes that are major source of electromagnetic interference (EMI). Such EMI problems may induce noise in the gating signals of the power switches, causing reliability problems. For example, if noise is induced in the gate of a nominally-off power switch and triggers the switch to turn on, the inverter leg may have a shoot-through or short-circuit situation. As one solution to this problem it is known to connect a snubber circuit consisting of resistor and capacitor to reduce the high di/dt and dv/dt of the switch so as to reduce the switching loss and stress. However, traditional snubber circuits are lossy because part of the switching loss is transferred from the switch to the snubber resistor. In order to achieve soft switching, it is necessary to create a zero voltage and/or zero current condition for the switch to turn on or off. If either the switch voltage or switch current is zero, the instantaneous product of switch voltage and current is zero. Thus, the switching loss becomes zero. In practice, it may not be possible to achieve absolute zero switch voltage and/or current. Instead, the switch voltage and/or current can be clamped to near-zero value. Such near-zero voltage and/or current zero-voltage and/or current switching may still be considered to be zero voltage or zero current. The general term for zero-voltage or zero-current switching is soft switching.
The following conditions have to be met in order to achieve soft switching in circuits including an inverter leg.
(A) For zero-voltage ‘turn off’ of power electronic switches S1 and S2
Condition (1)—Parallel capacitance is needed across the power switches S1 and S2 in order to limit the dv/dt of the switch so as to achieve zero-voltage turn off.
Parallel capacitance across the switch can come from the power switches' device capacitance such as the drain-source capacitance of the power mosfet. External capacitor can be added across the switch if necessary. This is a well known technique for zero-voltage turn off of power electronic devices.
(B) For zero-voltage ‘turn-on’ of power electronic switches S1 and S2
Condition (1*)—The tank current Iinput should be in the correct direction as follows:
For the inverter circuit example (FIG. 4), soft switching can be achieved if the overall load (including the resonant tank and resistive load) is inductive. The normal understanding in the prior art is that the frequency (fs) of the inverter's ac voltage Vinput must be higher that the dominant resonant frequency (fr) of the overall load so that the overall load is inductive. The actual soft-switching condition is that the current input is positive just before S2 (bottom switch) is turned on and negative just before S1 (top switch) is turned on (1*) (FIG. 6(a)). This is a necessary condition for zero-voltage switching
When S1 is turned off, it is soft-switched off because the parallel capacitor across S1 limits dv/dt of the switch voltage. The initial voltage across S1 is near zero during the turn-off process of S1. Therefore, S1 is zero-voltage (soft) turned off. The next important process is to ensure that S2 is soft-switched on. If fs>fr, the overall load is inductive. The existing method is to add a small dead time between the turn-off of S1 and turn-on of S2. During this dead time, both gating signals for S1 and S2 are off. However, this does not mean that the current Iinput is not continuous. When S1 is turned off, the capacitor voltage across S1 will rise to the dc rail voltage whilst the capacitor voltage across S2 will discharge to zero. Because the load is inductive, Iinput must be continuous. So the anti-parallel diode across S2 will be turned on so as to allow Iinput to flow continuously during this dead time. This means that the voltage across S2 will be clamped by its parallel diode's on-state voltage which is typically 0.7V (this is a near-zero-voltage when compared with the dc rail voltage of tens or hundreds of volts). Therefore, a soft-switching condition is created for S2 to be turned on at zero voltage condition.
Similar arguments apply to the soft-turn-off process of S2 and soft-turn-on process of S1. At the end of the on-time of S2, Iinput is negative. S2 can be soft turned off because of its parallel capacitor which limits the dv/dt of the voltage across S2. So S2 can be zero voltage (soft) turned off. S1 is not turned on immediately after S2 is turned off because of the dead time. The inductive load current Iinput has to flow into the anti-parallel diode of S1 during this dead time, thus clamping the voltage across S1 to zero. So S1 can be turned on under zero voltage condition.
The main problem of the above soft-switching method for the inverter circuit is that fs must be greater than fr so that the overall load is inductive. If fs<fr, the overall load becomes capacitive and the soft-switching condition that “the current Iinput is positive just before S2 is turned on and negative just before S1 is turned on” (1*) cannot be met (FIG. 6(b)). If Iinput is negative just before S2 is turned on, the anti-parallel diode of S2 is not conducting. Thus, the voltage across S2 is not clamped to zero for S2 to turn on and soft-switching condition is lost.
Condition (2*): Tank current Iinput must exceed a minimum magnitude in order to fully discharge total equivalent capacitance across the power switch for zero-voltage switching—Equation (3).
It is necessary to find the current threshold for soft switching in the operating frequency region. When the current is above the current threshold, soft switching can be achieved. The current iinput should be large enough to remove the charge on (discharge) the total equivalent capacitance across the power switch (such as the drain and source of the power mosfet). The requirement can be expressed by below equation:
                    Qs        =                                            ∫                                                -                                      t                    d                                                  /                2                                                              t                  d                                /                2                                      ⁢                                                            i                  input                                ⁡                                  (                  t                  )                                            ⁢                                                          ⁢                              ⅆ                t                                              ≥                      2            ⁢                                                  ⁢                          C              s                        ⁢                          V              g                                                          (        1        )            
where Qs is the charge and Cs is the total equivalent capacitance across the power switch (e.g. drain and source of the power switch), Vg is the dc inverter voltage and td is the dead time between the gating signals of S1 and S2.
If a resonant tank is used in the load circuit, the input circuit can be approximated as a sinusoidal current because of the filtering effect of the resonant tank.iinput(t)=Iinputsin (ωst−φ)  (2)
where Iinput is the peak magnitude of iinput(t), ωs=2πfs is the angular frequency of the inverter, t is the time variable and φ is the phase angle between the voltage generated by the inverter leg (Vinput) across the load circuit.
Based on (1) and (2), the input current must obey the following equation in order to create a zero-voltage condition for the power switch to achieve soft switching:Iinput≧CsVgωs/sin (ωs·td/2)  (3)
Therefore, equation (3) must be met as a necessary condition for soft switching. This equation provides a guideline to choose the appropriate td, Cs and fs.